1. Field of Invention
The present invention relates to a high storage capacity, wide data input/output channel, static random access memory (SRAM) device. More particularly, the present invention relates to a static random access memory device having 100 pins, a 64-bit data input/output channel and a 4 megabyte (4 Mbyte) storage capacity.
2. Description of Related Art
In the present information explosion era, personal computers have become indispensable tools in our daily lives. Personal computers help us in many ways, such as processing data, managing documents and transmitting information. At present, the main board of most personal computers either has a 256 KB or 512 KB cache memory for enhancing its memory function, and the cache memory is made up of SRAM chips.
A conventional SRAM having a 32-bit wide data input/output channel and 2Mbyte or 1 Mbyte storage capacity is generally assembled as a 100-pin integrated circuit (IC) and is packaged into either a quad flat package (QFP) or a thin quad flat package (TQFP). FIG. 1 shows the pin layout diagram of a conventional 32-bit data channel, 100 pins and 1 Mbyte SRAM. As shown in FIG. 1, this type of SRAM requires 1 clock pulse pin (CLK); 15 address pins (A0-A14); 32 data input/output pins (I/O 1-I/O 32); 6 write control pins (/BWE, /BW1-/BW4, /GW); 1 output control pin (/OE); 3 chip control pins (/CE1, /CE2, /CE3); 3 pipeline burst transmission control pins (/ADV, /ADSC, /ADSP); 1 burst transmission mode selection pin (/LBO); 1 fetch cycle mode control pin (/FT); 1 energy saving mode control pin (ZZ); 12 power pins (VDDQ/VDD); and 12 ground pins (VSSQJVSS). A total of 88 pins are used. The remaining 12 pins are no-contact pins (NC) and are there for future expansion.
For personal computers having a 512 KB main board cache memory, if memory can be accessed by a 32-bit wide data I/O channel, then two 2 Mbyte SRAM chips or four 1 MByte SRAM chips are required. But if memory can be accessed by a 64-bit wide data I/O channel, the cache memory can be implemented using one 4 Mbyte SRAM chip. Because one 4 Mbyte SRAM occupies less board area than either two 2 Mbyte SRAM or four 1 Mbyte SRAM, some main board area can be saved. However, due to the generation of a high output current when data is input or output through the 64-bit input/output data channel, delta I noises are created. These delta I noises may result in erroneous SRAM operations. To reduce interference caused by these delta I noises, more pins are normally necessary. FIG. 2 shows the pin layout diagram of a conventional 64-bit data channel, 128 pin, 2 Mbyte SRAM. As shown in FIG. 2, the SRAM requires 1 clock pulse pin (CLK); 15 address pins (A0-A14); 64 data input/output pins (I/O 1-I/O 64); 10 write control pins (BWE, BW1-BW8, GW); 1 output control pin (OE); 5 chip control pins (CE1, CE2, CE3, CE4, CE5); 3 pipeline burst transmission control pins (ADV, ADSC, ADSP); 1 burst mode control pin (MODE); 1 energy saving mode control pin (ZZ); 12 power pins (VCCQ/VCC); and 12 ground pins (GNDQ/GND). Of the total 128 pin, 125 pins are used. Only 3 pins are no-contact pins (NC) and are there for future expansion. Because the above SRAM has a larger number of pins, more main board area is needed for wiring. Moreover, the layout of the main board needs to be rescheduled and new testing procedures need to be implemented due to the extra pins, thereby increasing the cost of production. In light of the foregoing, there is a need in the art for improving the pin use and layout of the 64-bit, 128 pin, 4 Mbyte SRAM.